64#define Analog_Mux_0_chip_select 0x80
65#define Analog_Mux_1_chip_select 0x02
68#define Analog_Mux_maschera_quali_linee 0x07
69#define Analog_Mux_maschera_quale_chip (Analog_Mux_maschera_quali_linee +1)
70#define posizione_del_pattern_delle_linee 4
73#define MUX_analog_board_down 1<<5
74#define MUX_analog_postboard_0 0 << 3
75#define MUX_analog_postboard_1 1 << 3
76#define MUX_analog_postboard_2 2 << 3
77#define MUX_analog_postboard_3 3 << 3
79enum Mux_analog_postmainboard_lines_0{
80 Mux_analog_postmainboard_lines_0_Analog_Mux_2_out =MUX_analog_postboard_0,
81 Mux_analog_postmainboard_lines_0_Analog_Mux_1_out,
82 Mux_analog_postmainboard_lines_0_PRE_neg_1,
83 Mux_analog_postmainboard_lines_0_PRE_neg_2,
84 Mux_analog_postmainboard_lines_0_PRE_neg_3,
85 Mux_analog_postmainboard_lines_0_PRE_neg_4,
86 Mux_analog_postmainboard_lines_0_PRE_neg_5,
87 Mux_analog_postmainboard_lines_0_PRE_neg_6
90enum Mux_analog_postmainboard_lines_1{
91 Mux_analog_postmainboard_lines_1_PRE_pos_1 =MUX_analog_postboard_1,
92 Mux_analog_postmainboard_lines_1_PRE_pos_2,
93 Mux_analog_postmainboard_lines_1_PRE_pos_3,
94 Mux_analog_postmainboard_lines_1_PRE_pos_4,
95 Mux_analog_postmainboard_lines_1_PRE_pos_5,
96 Mux_analog_postmainboard_lines_1_PRE_pos_6,
97 Mux_analog_postmainboard_lines_1_SenseVreg_p,
98 Mux_analog_postmainboard_lines_1_SenseVreg_n
101enum Mux_analog_postmainboard_lines_2{
102 Mux_analog_postmainboard_lines_2_SenseGA =MUX_analog_postboard_2,
103 Mux_analog_postmainboard_lines_2_Vcc_meas,
104 Mux_analog_postmainboard_lines_2_PGA_Output_pos_1,
105 Mux_analog_postmainboard_lines_2_PGA_Output_pos_2,
106 Mux_analog_postmainboard_lines_2_PGA_Output_pos_3,
107 Mux_analog_postmainboard_lines_2_PGA_Output_pos_4,
108 Mux_analog_postmainboard_lines_2_PGA_Output_pos_5,
109 Mux_analog_postmainboard_lines_2_PGA_Output_pos_6
112enum Mux_analog_postmainboard_lines_3{
113 Mux_analog_postmainboard_lines_3_Vee_meas =MUX_analog_postboard_3,
114 Mux_analog_postmainboard_lines_3_Vdig_5V_meas,
115 Mux_analog_postmainboard_lines_3_PGA_Output_neg_1,
116 Mux_analog_postmainboard_lines_3_PGA_Output_neg_2,
117 Mux_analog_postmainboard_lines_3_PGA_Output_neg_3,
118 Mux_analog_postmainboard_lines_3_PGA_Output_neg_4,
119 Mux_analog_postmainboard_lines_3_PGA_Output_neg_5,
120 Mux_analog_postmainboard_lines_3_PGA_Output_neg_6
@ node_voltage_Analog_Mux_meas_bias_neg_ch2
@ node_voltage_Analog_Mux_meas_bias_pos_ch1
@ node_voltage_Analog_Mux_0_offset
Starting Offset for this set of nodes, 32.
@ node_voltage_Analog_Mux_meas_bias_neg_ch0
@ node_voltage_Analog_Mux_meas_bias_pos_ch2
@ node_voltage_Analog_Mux_meas_bias_pos_ch0
@ node_voltage_Analog_Mux_meas_bias_neg_ch3
@ node_voltage_Analog_Mux_meas_bias_pos_ch3
@ node_voltage_Analog_Mux_meas_bias_neg_ch1
void Analog_mux_line_to_select_deselect(uint8_t scheda_su_scheda_giu, uint8_t line_to_select, uint8_t select_1_deselect_0)
Selection of the line to mesure with the analog MUX of the mainboard, driven by the I2C->parallel mux...
@ node_voltage_Analog_Mux_1_res_fissa
Starting Offset for this set of nodes.
@ node_voltage_Analog_Mux_meas_10k_to_gnd
@ node_voltage_Analog_Mux_meas_none
void Analog_mux_line_to_select_deselect_for_postmainboard(uint8_t scheda_su_scheda_giu, uint8_t line_to_select, uint8_t select_1_deselect_0)
Selection of the line to measure with the analog MUX's of the postmainboard, directely driven by the ...
@ node_voltage_Analog_Mux_1_offset
Starting Offset for this set of nodes, 40.
@ node_voltage_Analog_Mux_meas_bias_pos_ch5
@ node_voltage_Analog_Mux_meas_bias_neg_ch5
@ node_voltage_Analog_Mux_meas_input_bias_neg
@ node_voltage_Analog_Mux_meas_bias_neg_ch4
@ node_voltage_Analog_Mux_meas_bias_pos_ch4
@ node_voltage_Analog_Mux_meas_input_bias_pos