DAC_PGA.c

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#include "tutti_gli_header.h"
 
/*****DOCUMENTAZIONE DOXYGEN             (premi il - a sinistra per ridurla a icona) il manuale html \'e nella cartella************/
/// \file
 
 
/*! \page  DAC_PGA_page  DAC_PGA
\brief <span style="color:red;"> <b> PGA Managing </b> </span>
*\tableofcontents
 
 \b SUMMARY:
*\arg \ref PGA_operation
*\arg \ref functions_not_for_user
*\arg \ref PGA_fw
 
*\section PGA_operation User use of PGA
<hr width="75%" size="10" align="left">
 
\n PGA is based on the <a href="./File_pdf/AD5451.pdf"  target=_blank><b>AD5451</b></a> a 10-bits DAC operated in feedback of
an Operational Amplifier, OA. This stage is preceded by another OA that can work at a voltage gain of 1 V/V or 10 V/V 
with a relay switchable gain setting. The input OA is set to its lower gain or larger gain if the set is smaller or larger than 10 V/V.
\n 3 functions have been developed, but only one is for the final user. The first function,  PGA_set_reset_pre_PGA_gain(), sets the gain of the input stage,
the second function sets the gain of the output stage only, PGA_DAC_GAIN_CROSS(), while the function for user, PGA_GAIN_CROSS(), set the gain of 
both stages according to to the value.
If we refer to the user functionn an example is quite useful:
 
<span style="color:orange;"> <I>
\code {.c}
PGA_GAIN_CROSS( scheda_su_scheda_giu,  canale,  PGA_gain_to_set  );
\endcode
</I> </span>
 
\note The minimum settable PGA gain is at #guadagno_minimo_PGA and now is "1 V/V", while the maximum settable PGA gain is at 
#massimo_guadagno_impostabile and now is "100 V/V". These limits are settable, but not from the user.
 
\n
\note PGA gain is stored at #PGA_settled_gain[12].
 
*\section functions_not_for_user Functions not for user
<hr width="75%" size="10" align="left">
\n The 2 functions PGA_set_reset_pre_PGA_gain() and PGA_DAC_GAIN_CROSS() are not directely usable from the user and can be individually used to 
study each single stage of the PGA. They can be set in order to consider a gain of "1 V/V" for the input stage irrispectively of the stage with the DAC
to study the noise constribution. Here an example of the atomic use of the 2 functions with an overal setting of 100 V/V, but with the input stage set at 1 V/V:
 
<span style="color:orange;"> <I>
\code {.c}
        PGA_set_reset_pre_PGA_gain ( scheda_su_scheda_giu,  canale_,  PGA_set_pre_pga_low_gain  )    ;
        PGA_DAC_GAIN_CROSS(scheda_su_scheda_giu,  canale_ , 1,100);
\endcode
</I> </span>        
 
*\section PGA_fw More details about PGA fw
<hr width="75%" size="10" align="left">
\n The user function is quite simple and obvious:
\snippetlineno DAC_PGA.c fun_PGA_GAIN_CROSS
 
\n For the setting of the first stage we need to set its relay. To implement the 2 signals we developed a
pair of swithes MOS-based that are driven by the 2 available digital signal from the detector bias trimmer chip, 
<a href="./File_pdf/AD5263.pdf"  target=_blank><b>AD5263 </b></a>, see the figure at 
\ref Figure_Trimmer_AD5263_per_relay, pin \b O1 and \b O2. The function PGA_set_reset_pre_PGA_gain() is given just below. 
Note that the input parameter \b set_2_reset_1_idle_0 is not the gain value. It is recommended to use the following definitions:
- #PGA_set_pre_pga_high_gain
- #PGA_set_pre_pga_low_gain
- #set_pre_pga_idle
 
*\snippetlineno DAC_PGA.c fun_PGA_set_reset_pre_PGA_gain
 
\n I2C is used in the function to manage the trimmer at set / reset the relay that provides the gain.
 
*\anchor Figure_Trimmer_AD5263_per_relay
*\image html AD5263_for_relay.png "FigureTrimmer_AD5263_per_relay: the 2 digital signals into evidence" width=40%
*\image latex AD5263_for_relay.png "FigureTrimmer_AD5263_per_relay: the 2 digital signals into evidence" width=40%
 
\n The DAC that vsets the gain of the second stage is managed with SPI and the function PGA_DAC_GAIN_CROSS() is:
\snippetlineno DAC_PGA.c fun_PGA_DAC_GAIN_CROSS
 
\n The codes for mamnaging the PGA gain are: 
 - \ref  DAC_PGA.c
 - \ref  DAC_PGA.h
 
*/
 
 
//Inizio CROSS
 
uint8_t guadagno_minimo_PGA= 1;    /*!< Minimum settable PGA gain, in V/V */
uint8_t massimo_guadagno_impostabile= 100 ; /*!< Maximum settable PGA gain, in V/V */
 
/*! \brief PGA set gain
*\snippet DAC_PGA.c vec_PGA_settled_gain
*/
//! <!-- [vec_PGA_settled_gain] -->
uint8_t PGA_settled_gain[12]={ 1, 1, 1, 1, 1,1,
                                                                1, 1, 1, 1, 1,1}; ///< PGA set gain
//! <!-- [vec_PGA_settled_gain] -->
                                                                
 /*! \brief Here the 2 digital signals from the trimmer are exploited to set the gain of the input stage of the PGA
 
*\param[in] scheda_su_scheda_giu One of the 2 boards that the postfrontend manages
*\param[in] canale                          The channel for which we need to manage the trimmer
*\param[in] PGA_gain_to_set             The overal gain to set                                                                  
*\return No Parameters
 
 *\snippetlineno DAC_PGA.c fun_PGA_GAIN_CROSS
 */
 //! <!-- [fun_PGA_GAIN_CROSS] -->
void PGA_GAIN_CROSS(uint8_t scheda_su_scheda_giu, uint8_t canale, uint8_t PGA_gain_to_set  ){
    uint8_t PGA_gain_for_second_stage=PGA_set_pre_pga_low_gain;
    uint8_t offset_schdea=0;
    if (scheda_su_scheda_giu){
        offset_schdea =6;
        scheda_su_scheda_giu=6;
    }
 
    
    PGA_settled_gain[canale + offset_schdea]= PGA_gain_to_set;
    if( PGA_gain_to_set >= PGA_pre_PGA_max_gain){
        PGA_set_reset_pre_PGA_gain ( scheda_su_scheda_giu,  canale,  PGA_set_pre_pga_high_gain  );//first stage of PGA at max gain
        PGA_gain_for_second_stage=PGA_pre_PGA_max_gain; //Communication of the gain set at first stega of PGA, to be used from PGA_DAC_GAIN_CROSS()
    }else{
        PGA_set_reset_pre_PGA_gain ( scheda_su_scheda_giu,  canale,  PGA_set_pre_pga_low_gain  );  //First stage of PGA at small gain
    }
    PGA_DAC_GAIN_CROSS( scheda_su_scheda_giu,   canale,  PGA_gain_to_set,  PGA_gain_for_second_stage);
    
//   int ciccia= ADC_lettura_registro(0,0,ADC_channel_conversion_time_FW_ch0_register);
    
}
 //! <!-- [fun_PGA_GAIN_CROSS] -->
 
 
 /*! \brief Here the 2 digital signals from the trimmer are exploited to set the gain of the input stage of the PGA
 
 *\param[in] scheda_su_scheda_giu one of the 2 boards that the postfrontend manages
 *\param[in] canale the channel for which we need to manage the trimmer
 *\param[in] set_2_reset_1_idle_0 if 1 the gain is at 10, if 0 the gain is 1                                                                        
 *\return No Parameters
 
 *\snippetlineno DAC_PGA.c fun_PGA_set_reset_pre_PGA_gain
 */
 //! <!-- [fun_PGA_set_reset_pre_PGA_gain] -->
void PGA_set_reset_pre_PGA_gain (uint8_t scheda_su_scheda_giu, uint8_t canale, uint8_t set_2_reset_1_idle_0  ){
    
        uint8_t spedizione[2];
        if( scheda_su_scheda_giu) scheda_su_scheda_giu=6;
 
        spedizione[1] = contenuto_trimmer_detector[canale + scheda_su_scheda_giu][0] ; //The trimmer content has to be 
                                                                    //written each time the digital signals are set/reset
      
    I2C_mux_select_ch(  scheda_su_scheda_giu, I2C_mainboard,   address_detector_bias_trimmer[canale].quale_I2C);  //Select the I2C to be used   
    
    if( set_2_reset_1_idle_0) {  //We operate only if we have to set
        
            spedizione[0] = set_2_reset_1_idle_0 << 1 ;  //The 2 bits are at position 1 and 2 of the byte
        
            
            I2C_mux->MasterTransmit( (uint8_t) address_detector_bias_trimmer[canale].indirizzo_I2C , spedizione, 2,false); //Write the selected trimmer of the selcted channel
            
            while( I2C_mux->GetStatus().busy);  // White transmission complete
            
            Aspetta_tanti_ms(wait_time_for_rele_setting);
            if(Error_bad_operation) ERROR_codifica_errore( scheda_su_scheda_giu, error_address_I2C0 , I2C_Error_trimmer_0  + canale,1);
    }       
        
        spedizione[0] =set_pre_pga_idle; // Both switches OFF, this operation is made always and can be made at the initialization
        
        I2C_mux->MasterTransmit( (uint8_t) address_detector_bias_trimmer[canale].indirizzo_I2C , spedizione, 1,false); ///Set the trimmer to read
        
        while( I2C_mux->GetStatus().busy);  // White transmission complete
        
        I2C_mux->MasterReceive( address_detector_bias_trimmer[canale].indirizzo_I2C, &tappo, 1,false);  //Read back, the trimmer value
        
        while( I2C_mux->GetStatus().busy){};
        
                contenuto_trimmer_detector[canale + scheda_su_scheda_giu][0]  = tappo;
}
 //! <!-- [fun_PGA_set_reset_pre_PGA_gain] -->  
 
 
/*! \brief It sets the PGA gain irrespective of the offset
 
*\param[in] scheda_su_scheda_giu is the board up or down
*\param[in] canale chi_aggiustiamo which channels to adjust
*\param[in] guadagno_da_impostare the gain to set
*\param[in] PGA_si_NO DAC PGA is not set if this parameter is 0
 
*\return   No Parameters.
 
*\snippetlineno DAC_PGA.c fun_PGA_DAC_GAIN_CROSS
*/
//! <!-- [fun_PGA_DAC_GAIN_CROSS] -->
void PGA_DAC_GAIN_CROSS(uint8_t scheda_su_scheda_giu,  uint8_t canale, uint8_t guadagno_da_impostare, uint8_t PGA_si_NO){
//      uint16_t    valore_da_trasmettere;
//  char ii;
//  uint8_t PGA_si_NO=1;
    
    //Attenzione: canale deve essere <6 
    uint8_t offset_scheda=0;
    if (scheda_su_scheda_giu){
        offset_scheda=6;
    }
//  valore_da_trasmettere = vettore_istruzioni[byte_istr_dati_0] + ( vettore_istruzioni[byte_istr_dati_1]<< 8);
    //Set the gain at the lower or maximum valued if the request is otside the limits
    if( guadagno_da_impostare<=guadagno_minimo_PGA) guadagno_da_impostare=guadagno_minimo_PGA ;
    if( guadagno_da_impostare > massimo_guadagno_impostabile ) guadagno_da_impostare =massimo_guadagno_impostabile ;
        PGA_settled_gain[canale + offset_scheda]= guadagno_da_impostare;
//  for(ii=0;ii<2;ii++){
//      if ( (canale >> ii) & 1) {  
//  if ( guadagno_da_impostare < gain_pre_PGA_x_2){
//      //Rele gain PGA a 1
//      Detector_PGA_Rele(  ( (ii<<4) | 8));
//  }else{
//      //Rele gain PGA a 1 o 10
//      if ( vettore_istruzioni[istruzione_byte_3] ){
//          // Gain PGA rele a 10
//          Detector_PGA_Rele(  ( (ii<<4) | 9));
//          PGA_si_NO=10;
//      }else{
//          // Gain PGA rele a 1
//          Detector_PGA_Rele(  ( (ii<<4) | 8));
//      }
//  }
//}
//}
 
    SPIdrv->Uninitialize();                             // Al DAC servono dati di 16 bit
    SPI_Inizialize_per_il_DAC();            //DAC operated at 16 bits
 
    //IL guadagno minimo del PGA al momento \'e 4, sta nella variabile guadagno_minimo_PGA
    uint16_t PGA_code =1+ (( (fondo_scala_DAC_PGA * guadagno_minimo_PGA) * PGA_si_NO) /  guadagno_da_impostare); //Gain to be set at the second stage of pga
    if ( PGA_code > 0x3ff) PGA_code=0x3ff;
    PGA_code = (PGA_code<<4) & 0x3FFF ;  //Il <<4 \'e la richiesat del dac
 
//  SPIdrv->Control(SPI_control_for_DAC, SPI_DAC_SPEED); // SPI fits DAC specs at 16 bits and speed
 
 
 
//  GPIO_PinWrite(local_pin_port.porta_num, local_pin_port.pin_num, 0);                             // Viene abbassato il Chip Sel del DAC del canale 0
// Dobbiamo aggiungere il chip select qui   
    I2C_to_Parallel_set_PCA9554_outputs_values(  scheda_su_scheda_giu,  PGA_DAC_chip_select[canale].I2C_to_parallel_chip_num, \
                                                PGA_DAC_chip_select[canale].I2C_to_parallel_chip__pin_num );
    Aspetta_tanti_ms(10);       
//  SPItx_16_per_il_DAC( (PGA_code<<4) & 0x3FFF);  //Il <<4 \'e la richiesat del dac
    SPIdrv->Send ( &PGA_code ,1); //send the 16 bits
//  while( SPIdrv->GetStatus().busy ){} //wait end of transmission
    Aspetta_tanti_ms(10);   // Bisogna aspettare almeno 5 ms prima di inviare un'altra istruzione   
 
            uint8_t troppa_attesa=0;
            while( (SPIdrv->GetStatus().busy) && (troppa_attesa <250) ){
                Aspetta_tanti_ms(1);
                troppa_attesa++;
            } //wait end of transmission     ;
            if((troppa_attesa>=250) || (Error_bad_operation)) ERROR_codifica_errore(scheda_su_scheda_giu, error_address_SPI, SPI_error_EVENT_DATA_LOST,1);
 
        
//  ERROR_codifica_errore( 0, error_address_SPI, Error_bad_operation, 1 );
//  GPIO_PinWrite(local_pin_port.porta_num, local_pin_port.pin_num, 1);                             // Viene alzato il Chip Sel del DAC del canale 0
// Dobbiamo aggiungere il chip un-select qui
    I2C_to_Parallel_set_PCA9554_outputs_values(  scheda_su_scheda_giu,  PGA_DAC_chip_select[canale].I2C_to_parallel_chip_num, \
                                                I2C_to_Parallel_ini_set[PGA_DAC_chip_select[canale].I2C_to_parallel_chip_num] );
    Aspetta_tanti_ms(10);                                                                           // Bisogna aspettare almeno 5 ms prima di inviare un'altra istruzione
    if(Error_bad_operation) ERROR_codifica_errore( scheda_su_scheda_giu, error_address_I2C0 , I2C_Error_I2C_to_parallel_PCA9554_0 + canale,1);
 
//  SPIdrv->Uninitialize(); // Si ritorna alla SPI a 8 bit
//  SPI_Inizialize();   
    //actual PGA gain
//  status = SPIdrv->Control(SPI_control_for_relay_driver,spi_clock_for_relais);
    SPIdrv->Uninitialize();                                                                     // Si ritorna alla SPI a 8 bit
    SPI_Inizialize();               
}
//! <!-- [fun_PGA_DAC_GAIN_CROSS] -->
 
 
//Fine CROSS
 
 
unsigned int PGA_Gain_code[2];
unsigned int PGA_Gain_V_su_V[2];
 
 
/*!  \brief It sets the PGA gain irrespective of the offset
 
*\param[in] scheda_su_scheda_giu is the board up or down
*\param[in] canale chi_aggiustiamo which channels to adjust
*\param[in] guadagno_da_impostare the gain to set
*\return   No Parameters.
 
*\snippetlineno DAC_PGA.c fun_PGA_GAIN
*/
//! <!-- [fun_PGA_GAIN] -->
void PGA_GAIN(uint8_t scheda_su_scheda_giu,  uint8_t canale, uint8_t guadagno_da_impostare){
//      uint16_t    valore_da_trasmettere;
//  char ii;
    uint8_t PGA_si_NO=1;
    
 
//  valore_da_trasmettere = vettore_istruzioni[byte_istr_dati_0] + ( vettore_istruzioni[byte_istr_dati_1]<< 8);
    if( guadagno_da_impostare<=guadagno_minimo_PGA) guadagno_da_impostare=guadagno_minimo_PGA ;
    if( guadagno_da_impostare > massimo_guadagno_impostabile ) guadagno_da_impostare =massimo_guadagno_impostabile ;
 
//  for(ii=0;ii<2;ii++){
//      if ( (canale >> ii) & 1) {  
//  if ( guadagno_da_impostare < gain_pre_PGA_x_2){
//      //Rele gain PGA a 1
//      Detector_PGA_Rele(  ( (ii<<4) | 8));
//  }else{
//      //Rele gain PGA a 1 o 10
//      if ( vettore_istruzioni[istruzione_byte_3] ){
//          // Gain PGA rele a 10
//          Detector_PGA_Rele(  ( (ii<<4) | 9));
//          PGA_si_NO=10;
//      }else{
//          // Gain PGA rele a 1
//          Detector_PGA_Rele(  ( (ii<<4) | 8));
//      }
//  }
//}
//}
    //IL guadagno minimo del PGA al momento \'e 4, sta nella variabile guadagno_minimo_PGA
    unsigned short PGA_code = ((fondo_scala_DAC_PGA * guadagno_minimo_PGA) * PGA_si_NO /  guadagno_da_impostare)   ;
 
 
    
    SPIdrv->Uninitialize();                             // Al DAC servono dati di 16 bit
    SPI_Inizialize_per_il_DAC();            //DAC operated at 16 bits
 
//  GPIO_PinWrite(local_pin_port.porta_num, local_pin_port.pin_num, 0);                             // Viene abbassato il Chip Sel del DAC del canale 0
// Dobbiamo aggiungere il chip select qui   
    I2C_to_Parallel_set_PCA9554_outputs_values(  scheda_su_scheda_giu,  PGA_DAC_chip_select[canale].I2C_to_parallel_chip_num, \
                                                PGA_DAC_chip_select[canale].I2C_to_parallel_chip__pin_num );
    Aspetta_tanti_ms(5);        
    SPItx_16_per_il_DAC( (PGA_code<<4) & 0x3FFF);  //Il <<4 \'e la richiesat del dac
    Aspetta_tanti_ms(10);                                                                           // Bisogna aspettare almeno 5 ms prima di inviare un'altra istruzione       
//  GPIO_PinWrite(local_pin_port.porta_num, local_pin_port.pin_num, 1);                             // Viene alzato il Chip Sel del DAC del canale 0
// Dobbiamo aggiungere il chip un-select qui
    I2C_to_Parallel_set_PCA9554_outputs_values(  scheda_su_scheda_giu,  PGA_DAC_chip_select[canale].I2C_to_parallel_chip_num, \
                                                I2C_to_Parallel_ini_set[PGA_DAC_chip_select[canale].I2C_to_parallel_chip_num] );
    Aspetta_tanti_ms(10);                                                                           // Bisogna aspettare almeno 5 ms prima di inviare un'altra istruzione
 
    SPIdrv->Uninitialize();                                                                     // Si ritorna alla SPI a 8 bit
    SPI_Inizialize();   
    //actual PGA gain
}
//! <!-- [fun_PGA_GAIN] -->
 
 
/*! \brief The second stage gain is settable here. 
 
This instruction needs to know the gain to set and the channel to apply the setting. These informztion are
at byte istruzione_byte_4_e_scelta_canale and at bytes byte_istr_dati_0 and byte_istr_dati_1 of the CAN message.
*\return   No Parameters, the actual result is sent to the CAN bus output throught \ref tx_data.
 
 
*\snippetlineno DAC_PGA.c fun_instruction_for_PGA_GAIN_set
*/
//! <!-- [fun_instruction_for_PGA_GAIN_set] -->
void instruction_for_PGA_GAIN_set(void){
    //This function must be optimized as it must opetrate with the x1 / x10 pre pga gain
    //vettore_istruzioni[1]=0 means channel 0, vettore_istruzioni[1]>0 means channel 1
    // vettore_istruzioni[2] is the MS8bits, while vettore_istruzioni[3] are the LS8bits 
    //of the gain to set.
    PGA_preparation_to_gain_set(vettore_istruzioni[istruzione_byte_4_e_scelta_canale],\
                                                                    vettore_istruzioni[byte_istr_dati_0] );
    
    tx_data[byte_istr_dati_0] = PGA_Gain_V_su_V[0];
    tx_data[byte_istr_dati_1] = PGA_Gain_V_su_V[1];
}
//! <!-- [fun_instruction_for_PGA_GAIN_set] -->
 
 
/*!  \brief It sets the new gain letting the output offset at the same level
 
 
*\param[in] chi_aggiustiamo which channels to adjust
*\param[in] guadagno_da_impostare the gain to set
*\return   No Parameters.
 
*\snippetlineno DAC_PGA.c fun_PGA_preparation_to_gain_set
*/
//! <!-- [fun_PGA_preparation_to_gain_set] -->
void PGA_preparation_to_gain_set(char chi_aggiustiamo, unsigned int guadagno_da_impostare){
        
    int misura_finale[2], offset;   
    char nodo_di_misura_1[]={ADC_ADC_PGA_neg_out_ch0, ADC_ADC_PGA_neg_out_ch1};
    char nodo_di_misura_2[]={ADC_ADC_PGA_pos_out_ch0, ADC_ADC_PGA_pos_out_ch1};
    int coarse_trimmer_step[] ={ coarse_Trimmer_offset_step_actual[0] * guadagno_minimo_PGA,coarse_Trimmer_offset_step_actual[1] * guadagno_minimo_PGA} ; //*********************************************
    int fine_trimmer_step[] = {fine_Trimmer_offset_step_actual[0] * guadagno_minimo_PGA, fine_Trimmer_offset_step_actual[1] * guadagno_minimo_PGA} ;     //*********************************************
    char canale;
    if (guadagno_da_impostare<guadagno_minimo_PGA) guadagno_da_impostare=guadagno_minimo_PGA;
    if( guadagno_da_impostare > massimo_guadagno_impostabile ) guadagno_da_impostare =massimo_guadagno_impostabile ;
    
    for( canale=0;canale<2;canale++){
        if( (chi_aggiustiamo >> canale) & 1){   
//          offset=lettura_ADC( nodo_di_misura_1[canale]) - lettura_ADC( nodo_di_misura_2[canale]); //Il <<1 \'e per renderlo differenziale
            valore_target_per_offset[canale]=correzione_misura_ADC(coeffcienti_misura_ADC_nodi[nodo_di_misura_1[canale]], offset);
            //Voglim mantenere la tenione allo stesso livello se \'e in scala, altrimenti aggiustiamo a zero
            if( (valore_target_per_offset[canale] >= saturazione_positiva) || ( valore_target_per_offset[canale] <= saturazione_negativa ) ) {
                valore_target_per_offset[canale]=0;
            }else{
            //Se il nuovo gain
            valore_target_per_offset[canale] = ( valore_target_per_offset[canale] * (int)guadagno_minimo_PGA ) / (int)guadagno_da_impostare ;
            }
 
        }
    }
    
PGA_GAIN_set(chi_aggiustiamo, 1);
 
    
//offset_Adjust_core( chi_aggiustiamo, valore_target_per_offset, nodo_di_misura_1, nodo_di_misura_2, \
//                                                                  ((fine_trimmer_step[0]+fine_trimmer_step[1])>>1), coarse_trimmer_step, fine_trimmer_step, 10, misura_finale);
    
PGA_GAIN_set(chi_aggiustiamo, guadagno_da_impostare);
    
    
    for( canale=0;canale<2;canale++){
        if( (chi_aggiustiamo >> canale) & 1){   
//          offset=lettura_ADC( nodo_di_misura_1[canale]) - lettura_ADC( nodo_di_misura_2[canale]); //Il <<1 \'e per renderlo differenziale
             offset=correzione_misura_ADC(coeffcienti_misura_ADC_nodi[nodo_di_misura_1[canale]], offset) * (int)guadagno_minimo_PGA / (int)guadagno_da_impostare ;
            int correzione =  (  valore_target_per_offset[canale]  - offset )  / (( (fine_trimmer_step[0]+fine_trimmer_step[1])>>1) ) ; 
            Trimmer_offset_preampli[canale].fine_offset= Trimmer_offset_preampli[canale].fine_offset - correzione;
            if (Trimmer_offset_preampli[canale].fine_offset >255) Trimmer_offset_preampli[canale].fine_offset=255;
            if( Trimmer_offset_preampli[canale].fine_offset <0 ) Trimmer_offset_preampli[canale].fine_offset=0;
            Imposta_canale_del_trimmer_ennesimo_al_valore_I2CA (canale, preampli_fine_offset_trimmer, Trimmer_offset_preampli[canale].fine_offset);     
        }
    }   
    
}
//! <!-- [fun_PGA_preparation_to_gain_set] -->
 
 
/*!  \brief It sets the new gain irrespective of the offset
 
 
*\param[in] canale which channels to adjust
*\param[in] guadagno_da_impostare the gain to set
*\return   No Parameters.
 
*\snippetlineno DAC_PGA.c fun_PGA_GAIN_set
*/
//! <!-- [fun_PGA_GAIN_set] -->
void PGA_GAIN_set(char canale, unsigned int guadagno_da_impostare){
//      uint16_t    valore_da_trasmettere;
    char ii;
    signed char PGA_si_NO=1;
    porta_pin_def local_pin_port;
 
//  valore_da_trasmettere = vettore_istruzioni[byte_istr_dati_0] + ( vettore_istruzioni[byte_istr_dati_1]<< 8);
    if( guadagno_da_impostare<=guadagno_minimo_PGA) guadagno_da_impostare=guadagno_minimo_PGA ;
    if( guadagno_da_impostare > massimo_guadagno_impostabile ) guadagno_da_impostare =massimo_guadagno_impostabile ;
 
    for(ii=0;ii<2;ii++){
        if ( (canale >> ii) & 1) {  
    if ( guadagno_da_impostare < gain_pre_PGA_x_2){
        //Rele gain PGA a 1
        Detector_PGA_Rele(  ( (ii<<4) | 8));
    }else{
        //Rele gain PGA a 1 o 10
        if ( vettore_istruzioni[istruzione_byte_3] ){
            // Gain PGA rele a 10
            Detector_PGA_Rele(  ( (ii<<4) | 9));
            PGA_si_NO=10;
        }else{
            // Gain PGA rele a 1
            Detector_PGA_Rele(  ( (ii<<4) | 8));
        }
    }
}
}
    
 
    //IL guadagno minimo del PGA al momento \'e 4, sta nella variabile guadagno_minimo_PGA
//  unsigned short int PGA_code = (guadagno_da_impostare << 7) / guadagno_minimo_PGA;
    unsigned short PGA_code = ((fondo_scala_DAC_PGA * guadagno_minimo_PGA) * PGA_si_NO /  guadagno_da_impostare)   ;
 
    
    for(ii=0;ii<2;ii++){
        if ( (canale >> ii) & 1) {
    if (ii==1 ){
        //Gain to set for channle 1
        local_pin_port=PGA_DAC_pin_select_ch1;
        PGA_Gain_code[1]= PGA_code;
        PGA_Gain_V_su_V[1]=guadagno_da_impostare;
    }else{
        //Gain to set for channle 0
        local_pin_port=PGA_DAC_pin_select_ch0;
        PGA_Gain_code[0]= PGA_code;
        PGA_Gain_V_su_V[0]=guadagno_da_impostare;
    }
    
    SPIdrv->Uninitialize();                             // Al DAC servono dati di 16 bit
    SPI_Inizialize_per_il_DAC();
 
    GPIO_PinWrite(local_pin_port.porta_num, local_pin_port.pin_num, 0);                             // Viene abbassato il Chip Sel del DAC del canale 0
    Aspetta_tanti_ms(5);        
    SPItx_16_per_il_DAC( (PGA_code<<4) & 0x3FFF);  //Il <<4 \'e la richiesat del dac
    Aspetta_tanti_ms(10);                                                                           // Bisogna aspettare almeno 5 ms prima di inviare un'altra istruzione       
    GPIO_PinWrite(local_pin_port.porta_num, local_pin_port.pin_num, 1);                             // Viene alzato il Chip Sel del DAC del canale 0
    Aspetta_tanti_ms(10);                                                                           // Bisogna aspettare almeno 5 ms prima di inviare un'altra istruzione
 
    SPIdrv->Uninitialize();                                                                     // Si ritorna alla SPI a 8 bit
    SPI_Inizialize();   
    //actual PGA gain
        }
        }
}
//! <!-- [fun_PGA_GAIN_set] -->