Mapping to mux's on postmainboard.
Mapping to mux's on postmainboard.
175Mux_analog_postmainboard_lines_2_PGA_Output_pos_1, Mux_analog_postmainboard_lines_2_PGA_Output_pos_2,
176Mux_analog_postmainboard_lines_2_PGA_Output_pos_3,Mux_analog_postmainboard_lines_2_PGA_Output_pos_4,
177Mux_analog_postmainboard_lines_2_PGA_Output_pos_5,Mux_analog_postmainboard_lines_2_PGA_Output_pos_6,
179Mux_analog_postmainboard_lines_3_PGA_Output_neg_1,Mux_analog_postmainboard_lines_3_PGA_Output_neg_2,
180Mux_analog_postmainboard_lines_3_PGA_Output_neg_3,Mux_analog_postmainboard_lines_3_PGA_Output_neg_4,
181Mux_analog_postmainboard_lines_3_PGA_Output_neg_5,Mux_analog_postmainboard_lines_3_PGA_Output_neg_6,
183Mux_analog_postmainboard_lines_1_PRE_pos_1,Mux_analog_postmainboard_lines_1_PRE_pos_2,
184Mux_analog_postmainboard_lines_1_PRE_pos_3,Mux_analog_postmainboard_lines_1_PRE_pos_4,
185Mux_analog_postmainboard_lines_1_PRE_pos_5,Mux_analog_postmainboard_lines_1_PRE_pos_6,
187Mux_analog_postmainboard_lines_0_PRE_neg_1,Mux_analog_postmainboard_lines_0_PRE_neg_2,
188Mux_analog_postmainboard_lines_0_PRE_neg_3,Mux_analog_postmainboard_lines_0_PRE_neg_4,
189Mux_analog_postmainboard_lines_0_PRE_neg_5,Mux_analog_postmainboard_lines_0_PRE_neg_6,
191Mux_analog_postmainboard_lines_2_Vcc_meas,
193Mux_analog_postmainboard_lines_3_Vee_meas,
195Mux_analog_postmainboard_lines_3_Vdig_5V_meas,
197Mux_analog_postmainboard_lines_1_SenseVreg_n,
199Mux_analog_postmainboard_lines_1_SenseVreg_p,
201Mux_analog_postmainboard_lines_2_SenseGA,
203Mux_analog_postmainboard_lines_0_Analog_Mux_1_out,
205Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,
207Mux_analog_postmainboard_lines_0_Analog_Mux_1_out,Mux_analog_postmainboard_lines_0_Analog_Mux_1_out,
208Mux_analog_postmainboard_lines_0_Analog_Mux_1_out,Mux_analog_postmainboard_lines_0_Analog_Mux_1_out,
209Mux_analog_postmainboard_lines_0_Analog_Mux_1_out,Mux_analog_postmainboard_lines_0_Analog_Mux_1_out,
210Mux_analog_postmainboard_lines_0_Analog_Mux_1_out,Mux_analog_postmainboard_lines_0_Analog_Mux_1_out,
212Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,
213Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,
214Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,
215Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,
217Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,
219Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,
221Mux_analog_postmainboard_lines_0_Analog_Mux_2_out,
223Mux_analog_postmainboard_lines_2_PGA_Output_pos_3};
const uint8_t ADC_node_map[]
Mapping to mux's on postmainboard. Its syntax: bits 0 to 3 are common to all the MUXs and select one ...